1. Field of the Invention
This invention describes a technique and method of formation of a DRAM array transistor which is in close proximity to a deep trench (DT) storage capacitor. The array cell device is formed using the Pad SiN, which is also used to create the shallow trench isolation (STI). The array device is self-aligned to the trench storage capacitor.
2. Description of the Related Art
Trench storage cells are used in DRAM products due to the high degree of planarity obtainable with the trench structure. One of the challenges associated with trench DRAM manufacturing, and integrated circuit manufacturing in general, is the control of the lithographic registration (alignment) between the various mask levels used to form the array.
The overlay tolerance required between masking levels is one factor which will limit the scaling of chip area by reduction of array cell size. For example, in a conventional process known as (MINT-BEST) Merged-Isolation
Node Trench cell with BuriEd STrap (Nesbit et al. IEDM 1993), lithographic masking levels are used to form the DT, the active area (AA) and the gate conductor (GC). A "buried strap" connection is then made between the top of the trench and the diffusion region. The buried strap eliminates the requirement for a distinct lithographic pattering level to connect the DT and the AA.
As DRAM chips increase in complexity, the area required to store each bit of data on the chip decreases and the area of the array is scaled with increasing DRAM bit counts per chip. A potential scaling limitation associated with the trench DRAM array cell structure is introduced by the area required for the pass transistor which is placed adjacent to the storage capacitor. Further, it is desirable to place the array pass transistor in close proximity to the trench storage capacitor, and thus decrease the area of the array cell.